搜索资源列表
I8253f_new
- I8253f的verilog实现，修正bug，经过DE2开发板下载实测可用。-I8253f the verilog implementation, amendment bug, measured through the DE2 development board is available to download.
DE2_USB_API
- altera d2e usb api example
clock_1Hz
- Clock 1Hz with duty cycle control for verilog for DE2-115 Altera FPGA
HW
- 关于 Altera DE2开发板上面的资料。各个控制模块的核心类容都在里面，采用Verilog 编写。-About Altera DE2 development board above information. Each control module is the core content classes are on the inside, written using Verilog.
tut_quartus_intro_verilog
- 为Quartus II和DE2新手准备的tutorial，Verilog版本.-Verilog edition tutorial for beginners
DE2_70_TV
- Verilog，DE2-70 TV范例，视频解码-An Example of convert dvd to video display moniter for DE2-70 in verilog
Verilog_zhinengdianti
- 很好的完善verilog代码，使用于智能电梯嵌入式开发和de2开发板爱好者-Very good perfect verilog code, used in intelligent elevator embedded development and de2 development board lovers
BCD-autoplus
- 利用Verilog HDL语言，编写一个2为BCD码加法器程序，并在DE2板是实现功能的运用。-Auto plus
DE2_TV(AV_VGA)
- 基于DE2-70的VGA图像处理，采用verilog语言编写-Based on the DE2-70 VGA image processing, using verilog language
Lab3
- This is stopwatch writen in Verilog HDL. Also there is code for 7-segment display decoder. I tested it on ALTERA de2-115 development and education board.
tut_DE2_sdram_verilog
- DE2 sdram 的verilog 教学材料-tut_DE2 sdram verilog.
DE0_exercise
- Altera公司生产的DE2开发板上附带资料的10个实验代码，在Quartus II环境下开发，绝对有价值（部分是在DE0上实现）-experiments of DE2 ,Altera,developmented with verilog
fre
- verilog hdl 开发的频率计，运行环境 DE2-115开发板，内有modelsim仿真用的testbench。RTL级代码-verilog hdl developed frequency meter, operating environment, the DE2-115 development board, modelsim simulation of the testbench. RTL-level code
timer
- 用verilog 实现时钟的功能，并在DE2开发板上调试-Clock with verilog and debug on the DE2 board
uart
- verilog VHDL实现的DE2 uart-Verilog VHDL the uart of the DE2
DE2_SD_Card_Audio
- 基于ALTERA公司DE2的读卡器驱动及音频处理（verilog）-ALTERA DE2 board, card reader drive and audio processing (verilog)
fpga-uart
- 基于DE2开发板的串口通信程序，使用Verilog HDL语言，-Serial communication program based on the DE2 board, using the Verilog HDL language
VDE22_NIOS_HOe
- Verilog代码，适合于初学入门者者进行学习，是一种基于DE2平台的代码。 -Verilog code, suitable for novice beginners to learn, a code based on the DE2 board.
VGA_Controller
- 由Verilog HDL编写的VGA控制器模块，可用于DE2板子。-For DE2 board VGA controller module written in Verilog HDL.
VerilogCode_time_of_day_clock
- Verilog Code for time-of-day clock and it is implemented on Altera DE2 board-Verilog Code for time-of-day clock and it is implemented on Altera DE2 board